1. Field of the Invention
The invention relates to a solid state imaging device and an electronic apparatus adapted to a camera or the like employing the solid state imaging device.
2. Description of the Related Art
As a solid state imaging device, there is known a CMOS solid state imaging device. Since the CMOS solid state imaging device has a low power source voltage and low power consumption, the CMOS solid state imaging device has been used for a digital still camera, a digital video camera, and various types of mobile terminals such as a mobile phone attached with a camera attached.
The CMOS solid state imaging device includes a pixel portion where a plurality of pixels including photodiodes as photoelectric conversion portions and a plurality of pixel transistors are disposed in a two-dimensional array shape with regularity and a peripheral circuit portion which is disposed in the vicinity of the pixel portion.
In general, in a front illumination type CMOS solid state imaging device in the related art, the interval between the wiring lines is configured to be an interval defined by the minimum design rule so that the wiring lines provided to the pixel portion are not disposed to pass over the photodiodes which are photoelectric conversion portions in the optical point of view.
In the front illumination type CMOS solid state imaging device, generally, in the case where the accumulating time is long or in the case where an amount of incident light is large, the accumulated charges of the photodiode exceeds the capacitance of the photodiode so as to overflow, so that a so-called blooming phenomenon occurs, which causes deterioration of image quality. Therefore, in order to prevent the blooming, a so-called vertical overflow structure of releasing charges to a substrate has been configured. In other words, in the situation where the transfer gate is turned off, the potential is designed to be lowered, so that a decrease in a saturation signal amount Qs is prevented, and almost no influence is designed to be exerted to the potential change of the preceding transfer gate, so that a variation in the saturation signal amount is avoided.
In addition, recently, a back illumination type CMOS solid state imaging device has drawn attention (refer to Japanese Unexamined Patent Application Publication Nos. 2007-115994 and 2003-31785). In the back illumination type CMOS solid state imaging device, light is incident to a rear surface of a substrate at a side opposing the side where wiring lines are disposed, and the wiring lines of a pixel portion may be disposed to pass over photodiodes, so that a degree of freedom in the layout is greatly increased. In involvement with miniaturization of a pixel size, a pixel sharing type CMOS solid state imaging device where one pixel transistor group excluding transfer transistors is shared by a plurality of photodiodes is also disclosed (refer to Japanese Unexamined Patent Application Publication Nos. 2008-294218 and 2009-135319)
Until the pixel size is decreased down to about 1.5 μm, the layout may be implemented by configured the interval between the wiring lines not so as to be narrowed by using the pixel sharing type. In addition, in the back illumination type CMOS solid state imaging device, in general, the lateral overflow is formed as an approach for countering the blooming. In the lateral overflow, charges are allowed to be released through the floating diffusion portion from a portion under the transfer gate. In the back illumination type CMOS solid state imaging device, there is a disadvantage in the potential change of the transfer gate due to the influence of the lateral overflow structure. However, in the case where the pixel size is large, the interval between the transfer wiring lines may be configured to be relatively large, or the pixel sharing type, where the maximum pixel aperture ratio may not be obtained but the interval between the transfer wiring lines may be easily taken, has been employed to obtain relatively small coupling between the transfer wiring lines, so that the aforementioned problem has been avoided. In other words, if the pixel size is large, the interval between the wiring lines may not be narrowed, so that no problem occurs in that signal loss due to the potential change of the transfer gate according to the coupling between the transfer wiring lines. In addition, the pixel sharing type is configured so vertical four pixels are shared without narrowing the interval between the transfer wiring lines, so that no problem is caused by signal loss due to the potential change of the transfer gate.